As semiconductor device sizes move toward the submicron regime, the challenges associated with particulate microcontamination present substantial hurdles to success. Advances in semiconductor processing are needed to ensure that manufacturing efficiencies can be kept high. In particular, improved performance-at-yield and significant increases in wafer throughput (e.g., more than 160 of 200 mm wafers/hr) are desired to reduce unit costs. The emerging applications for nanotechnologies also require special cleaning, and new deposition methods and materials will be required. In an industry driven by device yield, reliability, and performance criteria, substrate cleaning has become particularly important for efficiency and profitability.
Processing of advanced semiconductor materials, e.g., plasma etching, deposition, or chemical mechanical polishing, can leave residues (particle, ionic, or both) that are difficult to remove with conventional cleaning processes (such as wet benches, spray tools, etc). Critical residue particle sizes continue to decrease to below 20 nm, yet conventional particle removal methods (spray, ultrasonic, and megasonics) are ineffective, will damage the desired submicron structural features, or both.
As submicron processing advances, it becomes important to remove or neutralize etching residue and photoresist from the substrate, for example so that the residues do not absorb moisture and form acidic species that can cause undesired metal corrosion. If such metal residues are not removed, the substrate's devices may short. In addition, plasma etching of metals, for example, results in a variety of residues, and presents the challenge of adequately cleaning surface(s) of a substrate without corroding the metal.
Moreover, there is a thrust within the semiconductor industry to significantly reduce chemical and water consumption for both cost control and environmental concerns. Water consumption has been a growing concern in both the US and European markets. Although the industry is adapting cleaning chemistries with higher water content, the overall requirements are for semiconductor facilities to reduce total water consumption. Some alternative technologies contemplated for use are based on supercritical CO2 with co-solvents, cryogenics, plasma, laser shock, ion beam, or UV/ozone processes.
Despite the work done, for example, with supercritical CO2, laser shock waves, and UV ozone, each of these technologies has experienced significant technical barriers. Supercritical CO2 currently requires the use of co-solvents and controlled rinse sequences at pressures up to 3,000 psi. Yet, the goals of elimination of secondary deposition of particles and reduction of cycle times below 5 minutes have not been achieved. For example, laser shock (the convergence of two laser beams at some distance from the wafer surface) can easily damage wafer surfaces and carries the additional requirement that the wafer be processed through a traditional wet cleaning step in order to be able to remove ionic contamination. The UV ozone process is designed to generate high-energy free radical species to scavenge organic residues, but remains largely unproven for mainstream application.
During the late 1980's, combined government/industry programs were started to develop semiconductor fabrication processes that required few or no liquid chemical processing steps. The programs were not able to achieve these goals though they were able to further establish the benefits of plasma etch over wet etch of integrated circuit (IC) features. Newer technologies have been contemplated to minimize the cleaning challenges and include direct-imageable materials and in-situ/in-step post processing. The semiconductor industry continues to support research in this direction (see, e.g., Solid State Technology, March 1999, S13; Semiconductor Online, Mar. 2, 1999). However, incomplete removal of ionic species and particle contamination continue to be pressing issues. Various matured technologies for the production of a clean and dry 90 nm node copper semiconductor wafer with ultra low-k dielectrics, for example, have failed to meet expectations (according to the ITRS 2002).
Attempts have been made with current plasma etch equipment to program, design or adjust process parameters to minimize or eliminate post-etch residues, but because of the newer materials (cobalt silicides, Cu, low-k materials, HfO2, ZrO2, Pt, Ru, etc.) and the increasing aspect ratios and reduced particle sizes, these efforts have not met the current cleaning requirements. Conventional wet chemical cleaning methods also have not been able to meet some of these requirements.
Mist deposition of films on substrates also is known. See P. Mumbauer et al., Mist Deposition in Semiconductor Device Manufacturing, Semiconductor International, dated Nov. 1, 2004.
High throughput semiconductor cleaning processes are needed for providing high particle removal efficiency (PRE) while minimizing damage or undesired etching. See Steven Verhaverbeke (Applied Materials), “An Investigation of the Critical Parameters of a Atomized, Accelerated Liquid Spray to Remove Particles,” presented at the 208th Meeting of the Electrochemical Society, Los Angeles, Calif., Oct. 16-21, 2005, symposium on Cleaning Technology in Semiconductor Device Manufacturing IX, Electronics and Photonics/Dielectric Science and Technology; see also Ken-Ichi Sano et al. (Dainippon Screen and IMEC), “Single Wafer Wet Cleaning for a High Particle Removal Efficiency on Hydrophobic Surface,” also presented at the 208th Meeting of the Electrochemical Society. Verhaverbeke reported the use of atomized, accelerated liquid sprays to remove particles in which the gas velocities used to accelerate the liquid droplets approached 50 m/s. Sano et al. reported the use of a two-step single wafer cleaning process.
Conventional spray cleaning processes typically employ nozzles disposed between about 45° and about 90° with respect to the wafer surface. Conventional cryogenic cleaning processes typically employ nozzles disposed between about 75° and about 90° with respect to the wafer surface. High speed wet cleaning has been limited below 100 m/s, thus well below supersonic speeds (about 360 m/s).
In view of these developments, there is a need for chemistry that can be used in the reaction/removal of contaminants on a substrate. There further is a need for chemistry that may encapsulate particles. Moreover, there is a need for chemistry that permits acceptable drying of a substrate after application. Also, there is a need for chemistry that may remove substantially all trace residuals to below 4 nm detection levels at less than 50 ppb without damage or impounding of contaminants into the substrate. In addition, there is a need for methods and apparatus for delivering the chemistry in a precisely controlled fashion. And, there is a need for processing with reduced water and chemical consumption as compared to the mainstream technologies of the prior art. There additionally is a need for such processing at atmospheric or near-atmospheric conditions instead of the high vacuum conditions required by prior art processes.